1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a horizontal bipolar transistor.
2. Description of the Prior Art
In general, when a composite device such as IIL (Integrated Injection Logic) is formed, a vertical npn transistor and a lateral pnp transistor, for instance are both manufactured under coexistence condition. In this case, the lateral pnp transistor is formed in accordance with the process of forming the vertical npn transistor.
FIGS. 4A and 4B show an example of the composite device. In FIGS. 4A and 4B, the lateral pnp transistor is formed as follows: An n-type impurity region of high concentration (e.g., 1.times.10.sup.19 cm.sup.-3) is formed in a silicon substrate 19 as an N-type buried layer 20; a collector epitaxial layer 21 is grown on the n-type buried layer 20; and the formed epitaxial layer 21 is insulated and separated by an insulation separating layer 22 formed of an oxide film. Successively, an oxide film 23 and a nitride film 24 are both deposited all over the substrate in sequence. Further, the formed nitride film 24 is patterned to a predetermined shape. After that, an emitter region 25 is formed by implanting B or BF.sub.2 ions at a dose of about 1.times.10.sup.16 cm.sup.-2. Further, a collector region 26 is formed by implanting B or BF.sub.2 ions at a dose of about 1.times.10.sup.13 cm.sup.-2. Therefore, as described above, a part of the epitaxial layer 21 can be formed as a base region 27. After that, after an interlayer insulating film 29 has been formed by use of the well-known technique, contact holes are opened; the opened contact holes are buried by a metal film; the metal electrodes are formed to form metal electrodes; and then an emitter electrode 30, a base electrode 31 and a collector electrode 32 are formed to complete a transistor.
In the transistor manufactured as described above, since the width of the base thereof is decided on the basis of the precision of the photolithography, it has been so far limited to use the formed transistor for a high speed circuit. In addition, since the minority carriers injected from the lower surface of the emitter region 25 do not reach the collector region 26, there exists a problem in that the current gain is reduced.
In other words, since the base width of the lateral pnp transistor is decided by the limit of the photolithography, it is difficult to reduce the base width down to about 0.1 .mu.m or less by the present processing technique, so that the formed transistor cannot be operated at a high speed. Further, since the emitter region 25 and the collector region 26 are both formed separately by the different photolithography process, there exists another problem in that the manufacturing cost is relatively high.
Further, FIG. 5 shows an example of prior art Bi-CMOS transistors. In the Bi-CMOS transistors, a bipolar transistor of high operational speed and a CMOS transistor of easy integration are combined with each other in general. In the Bi-CMOS transistor, however, since the manufacturing process is generally complicated, there exists such a shortcoming that the manufacturing cost thereof is relatively high. To overcome this problem, a low-cost Bi-CMOS transistor as shown in FIG. 5 has been proposed, in which a MOS transistor is substituted for a bipolar transistor. In this case, for instance, a base region 53 of a pnp type bipolar portion is formed in the same way as with the case of an N-well 56 of a pMOS transistor, and further an emitter region 73a and a collector region 73b are formed in the same way as with the case of a source region 68a and a drain region 68b of a pMOS transistor, respectively.
In the Bi-CMOS transistor as described above, since the manufacturing process can be simplified, it is possible to reduce the manufacturing cost thereof. In this method, however, since the thickness of the base layer of the bipolar transistor cannot be reduced, there exists a problem in that the high speed operation is not enabled. Further, since the breakdown voltage of the bipolar portion is relatively low, there exists another problem in that the reliability of the element is low. In addition, in the same way as with the case of the prior art lateral bipolar transistor as shown in FIGS. 4A and 4B, a problem arises in that the current gain thereof is also low.